Magnetic memory device

A method, comprising:

• storing first initial logical values in an arranged pattern in a magnetic sensing array comprising a plurality of magnetic sensing elements;
• sensing an external magnetic field strength based on a flip rate of the first initial logical values;
• providing a test voltage different from a current write voltage of the magnetic memory device using a voltage modulator, in response to the external magnetic field strength being greater than a threshold magnetic field strength;
• storing a plurality of error check elements with second initial logical values;
• reading the second initial logical values of the plurality of error check elements;
• writing a same logical value to each error check element of the plurality of error check elements using the test voltage as a write voltage;
• comparing written logical values of the plurality of error check elements with the second initial logical values to calculate a bit error rate corresponding to the test voltage;
• and
• adjusting a write voltage of the magnetic memory device from the current write voltage to the test voltage, based on the bit error rate being equal to or less than a threshold bit error rate.

A magnetic memory device, comprising:

• a storage array comprising a plurality of storage elements, wherein each storage element of the plurality of storage elements comprises a magnetic tunnel junction and one or more transistors, and wherein the magnetic tunnel junction is interposed between two metal layers of each storage element;
• a magnetic sensing array comprising a plurality of magnetic sensing elements, wherein the magnetic sensing array is configured to sense an external magnetic field strength based on a flip rate of first initial logical values;
• a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device;
• an error check array comprising a plurality of error check elements with second initial logical values;
• and
• a control device configured to compare the bit error rate to a threshold bit error rate.