Shift register having low power mode

Abstract

The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Dependencies are inferred from the claim text.