Three-dimensional flash memory for improving integration and operation method thereof

An erase operation method of a three-dimensional flash memory having a structure in which a Ground Selection Line (GSL) is removed by including a plurality of word lines which are formed by extending in a horizontal direction on a substrate and are sequentially stacked and a plurality of strings passing through the plurality of word lines and formed by extending in one direction on the substrate, each of the plurality of strings including a channel layer formed by extending in the one direction and a charge storage layer formed by extending in the one direction to surround the channel layer, and the channel layer and the charge storage layer constituting a plurality of memory cells corresponding to the plurality of word lines, and the channel layer including a back gate formed by extending in the one direction while at least a part thereof is surrounded by the channel layer and an insulation film formed by extending in the one direction between the back gate and the channel layer, the erase operation method comprising:

• grounding remaining word lines except for a word line located at the lowermost end among the plurality of word lines;
• and
• performing an erase operation on the plurality of strings by applying a Gate-Induced Drain Leakage (GIDL) voltage for causing GIDL phenomenon to the word line located at the lowermost end, at least one String Selection Line (SSL) located above the plurality of word lines, bit lines of a plurality of strings, and a common source line (CSL).