Semiconductor memory device with first and second sense amplifiers

A semiconductor memory device comprising:

• a first word line extending in a first direction;
• a first memory cell capable of storing data of at least two bits, a gate of the first memory cell being connected to the first word line;
• a second memory cell capable of storing data of at least two bits, a gate of the second memory cell being connected to the first word line, the second memory cell being positioned at one side in the first direction with respect to the first memory cell;
• a first bit line connected to the first memory cell, the first bit line extending in a second direction, the second direction crossing the first direction;
• a second bit line connected to the second memory cell, the second bit line extending in the second direction;
• a first sense amplifier including a first transistor, the first transistor being connected to the first bit line;
• and
• a second sense amplifier including a second transistor, the second transistor being connected to the second bit line,
• wherein
• during a read operation to judge the data stored in the first memory cell and the second memory cell,
• a voltage at a gate of the first transistor is increased to a first voltage, and decreased to a second voltage,
• a voltage at a gate of the second transistor is increased to a third voltage, and decreased to a fourth voltage, and
• a strobe signal is applied to the first sense amplifier and the second sense amplifier in a state where the second voltage is applied to the gate of the first transistor and the fourth voltage is applied to the gate of the second transistor, and
• at least the voltage at the gate of the second transistor is gradually decreased from the third voltage to the fourth voltage with a gradient more gentle than a gradient when the voltage at the gate of the second transistor is increased to the third voltage.