Semiconductor storage device

A semiconductor storage device, comprising:

• a bit line;
• a source line;
• a plurality of depletion-type memory cell transistors of an n-type connected in series between the bit line and the source line;
• and
• a control circuit configured to program the memory cell transistors to one of a plurality of write states in response to an instruction from an external controller, wherein
• the plurality of threshold voltage distributions include a first threshold voltage distribution corresponding to one of the write states and a second threshold voltage distribution corresponding to another one of the write states, and
• all voltages of the first threshold voltage distributions are less than 0 V.

A semiconductor storage device, comprising:

• a bit line;
• a source line;
• a plurality of depletion-type memory cell transistors of a p-type connected in series between the bit line and the source line;
• and
• a control circuit configured to program the memory cell transistors to one of a plurality of write states in response to an instruction from an external controller, wherein
• the plurality of threshold voltage distributions include a first threshold voltage distribution corresponding to one of the write states and a second threshold voltage distribution corresponding to another one of the write states, and
• all voltages of the first threshold voltage distributions are greater than 0 V.