Die by die trimming of drain-side select gate threshold voltage to reduce cumulative read disturb

A controller in communication with a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the controller configured to:

• select the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells;
• and
• instruct the memory apparatus to program the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.

A method of operating a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the method comprising the steps of:

• selecting the transistor threshold voltage of the drain-side select gate transistors as a stable transistor threshold voltage for a grouping of the memory cells to minimize shifting of the transistor threshold voltage following a plurality of read operations of the memory cells;
• and
• programing the transistor threshold voltage of the drain-side select gate transistor of the plurality of memory holes associated with the grouping of the memory cells to the stable transistor threshold voltage.