Memory device including row decoder

A memory device comprising:

• a first semiconductor structure including a substrate which includes first and second cell regions adjacent to each other in a first direction and a row decoder region between the first cell region and the second cell region, a peripheral circuit which is defined in the first and second cell regions of the substrate, a plurality of pass transistors which are defined in the row decoder region of the substrate, a first bonding layer which includes a plurality of first bonding pads, and a plurality of at least three bottom wiring layers which are disposed between the substrate and the first bonding layer;
• a second semiconductor structure disposed on the first semiconductor structure, and including a second bonding layer which includes a plurality of second bonding pads bonded to the plurality of first bonding pads, a memory cell array, and at least one top wiring layer which is disposed between the second bonding layer and the memory cell array;
• and
• a plurality of global lines disposed in the row decoder region, and configured to transfer operating voltages to the plurality of pass transistors,
• wherein the plurality of global lines are disposed in at least one of a first bottom wiring layer which is positioned at a lowermost part among the plurality of bottom wiring layers and a second bottom wiring layer immediately over the first bottom wiring layer.