US 2023/0410908 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

According to one embodiment, a semiconductor memory device includes first, second, third and fourth word lines coupled to first, second, third and fourth memory cells, respectively. A first transistor includes a first gate and is electrically coupled to the first word line. A second transistor includes a second gate and is electrically coupled to the second word line. A third transistor includes a third gate and is electrically coupled to the third word line. A fourth transistor includes a fourth gate and is electrically coupled to the fourth word line. The first gate is included in a first conductive layer. The second gate is included in a second conductive layer arranged away from the first conductive layer. The third and fourth gates are included in a third conductive layer which is integral and continuous.

Claims20

Dependent claims

A semiconductor memory device comprising:

a first word line coupled to a first memory cell;
a second word line coupled to a second memory cell;
a third word line coupled to a third memory cell;
a fourth word line coupled to a fourth memory cell;
a first transistor including a first gate and electrically coupled to the first word line;
a second transistor including a second gate and electrically coupled to the second word line;
a third transistor including a third gate and electrically coupled to the third word line;
and
a fourth transistor including a fourth gate and electrically coupled to the fourth word line,
wherein
the first gate is included in a first conductive layer,
the second gate is included in a second conductive layer arranged away from the first conductive layer, and
the third gate and the fourth gate are included in a third conductive layer which is integral and continuous.

10 more elements

A semiconductor memory device comprising:

a first word line coupled to a first memory cell;
a second word line coupled to a second memory cell;
a third word line coupled to a third memory cell;
a fourth word line coupled to a fourth memory cell;
a fifth word line coupled to a fifth memory cell;
a sixth word line coupled to a sixth memory cell;
a first transistor including a first gate and electrically coupled to the first word line;
a second transistor including a second gate and electrically coupled to the second word line;
a third transistor including a third gate and electrically coupled to the third word line;
a fourth transistor including a fourth gate and electrically coupled to the fourth word line;
a fifth transistor including a fifth gate and electrically coupled to the fifth word line;
and
a sixth transistor including a sixth gate and electrically coupled to the sixth word line, wherein
the first gate is included in a first conductive layer,
the second gate is included in a second conductive layer arranged away from the first conductive layer,
the third gate and the fourth gate are included in a third conductive layer which is integral and continuous,
the fifth gate is included in a fourth conductive layer, and
the sixth gate is included in a fifth conductive layer arranged away from the fourth conductive layer.

15 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20