Split footer topology to improve vmin and leakage power for register file and read only memory designs

An apparatus, comprising:

• a memory device to store instructions;
• and
• a processor to execute the instructions to perform a read operation for a selected memory cell in a selected column of memory cells in an array, wherein:
• the selected column of memory cells is coupled to a bit line;
• a respective column select transistor is coupled to the bit line;
• a respective footer transistor is coupled to each memory cell in the selected column of memory cells;
• and
• to perform the read operation, the processor is to apply a turn on voltage to the respective footer transistor and the respective column select transistor of the selected column of memory cells, apply a turn off voltage to respective footer transistors and respective column select transistors of unselected column of memory cells in the array and increase a voltage on a selected word line.