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US 2023/0410897 A1Published application
Asymmetrical Memory Circuits And Methods
AssigneeIntel Corporation
InventorsDavid Parkhouse, Andy Lee, J M Lewis Higgins, Yan Cui, Shuxian Chen, Shankar Sinha
Life of this patent
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Abstract
A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.
Claims20
A memory circuit comprising:
- first and second inverters that are cross coupled, wherein the first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit, and wherein the first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.
A method for storing data in a memory circuit, the method comprising:
- providing a first drive current through a first inverter from a first supply line to store a first logic state in the memory circuit;
- and
- providing a second drive current through a second inverter from the first supply line to store a second logic state in the memory circuit, wherein the first drive current is larger than the second drive current.
A storage circuit comprising:
- first and second inverters, wherein the first inverter comprises one or more first transistors coupled between a first supply line and a first node in the storage circuit, wherein the second inverter comprises a second transistor coupled between the first supply line and a second node in the storage circuit, and wherein the one or more first transistors have a larger size than the second transistor.
Dependencies are inferred from the claim text.