Semiconductor element memory device

A semiconductor element memory device comprising either or both of a first block and a second block,

• the first block including a plurality of first memory cells arranged in a matrix, each first memory cell being formed of one semiconductor element,
• the second block including a plurality of second memory cells arranged in a matrix, each second memory cell being formed of two semiconductor elements,
• each semiconductor element including:
• a semiconductor base standing on a substrate in a vertical direction with respect to the substrate or extending on the substrate in a horizontal direction with respect to the substrate;
• a first impurity region and a second impurity region at both ends of the semiconductor base;
• a gate insulating layer that is in contact with a side surface of the semiconductor base between the first impurity region and the second impurity region;
• a first gate conductor layer that covers a part or an entirety of the gate insulating layer;
• and
• a second gate conductor layer that is adjacent to the first gate conductor layer and that is in contact with a side surface of the gate insulating layer, wherein
• the semiconductor element memory device is configured to perform a memory write operation of controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region to hold, inside the semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current and to cause the semiconductor base to have a first data retention voltage,
• the semiconductor element memory device is configured to perform a memory erase operation of controlling voltages to be applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer to discharge the positive hole group from either or both of the first impurity region and the second impurity region and to cause the semiconductor base to have a second data retention voltage lower than the first data retention voltage,
• in the first block, the first impurity region is connected to a source line, the second impurity region is connected to an odd-numbered bit line or an even-numbered bit line in an alternating manner, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, an other of the first gate conductor layer and the second gate conductor layer is connected to a first drive control line, and the semiconductor element memory device is configured to, in accordance with voltages to be applied to the source line, the bit lines, the first drive control line, and the word line, fix one of the odd-numbered bit line and the even-numbered bit line to a first voltage and read data stored in the first memory cell through an other of the odd-numbered bit line and the even-numbered bit line,
• in the second block, the second memory cell includes an odd-numbered memory cell formed of a semiconductor element connected to the odd-numbered bit line and an even-numbered memory cell formed of a semiconductor element connected to the even-numbered bit line adjacent to the odd-numbered bit line, and
• the number of first blocks and the number of second blocks are variable in the semiconductor element memory device that is in operation.