Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)

An in-memory computation circuit, comprising:

• a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line connected to the memory cells of the column;
• a word line driver circuit for each row having an output connected to drive the word line of the row, wherein the word line driver circuit is powered by an adaptive supply voltage dependent on integrated circuit process and/or temperature conditions;
• a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation;
• and
• a column processing circuit including a first read circuit coupled to each first bit line, wherein each first read circuit comprises:
• a first current mirroring circuit configured to mirror a first read current on the first bit line to generate a first mirrored read current;
• and
• a first integration capacitor configured to integrate the first mirrored read current to generate a first output voltage;
• wherein the adaptive supply voltage and configuration of the first current mirroring circuit inhibits drop of a voltage on the first bit line below a bit flip voltage during the simultaneous actuation of the plurality of word lines for the in-memory compute operation.