Memory driver, memory system, and operating method

A memory system, comprising:

• a memory array comprising a plurality of memory cells controlled by a plurality of word lines;
• and
• a memory driver, comprising:
• a word line driver circuit coupled to the plurality of word lines and configured to selectively provide a reference voltage from a reference node to a selected word line of the plurality of word lines according to an input signal;
• a reference circuit comprising a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor, to cause charge sharing according to a capacitance of the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line;
• and
• a bias circuit coupled to the reference node and configured to regulate the reference voltage after the reference voltage is provided from the reference node to the selected word line.

An operating method for operating a memory array, the memory array comprising a plurality of memory cells controlled by a plurality of word lines, the operating method comprising:

• storing a reference voltage on a capacitor and coupling the capacitor to a reference node to provide the reference voltage to the reference node;
• selectively providing the reference voltage to a selected word line of the plurality of word lines;
• lowering the reference voltage from a first voltage level to a second voltage level by voltage sharing between the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided from the reference node to the selected word line of the plurality of word lines;
• and
• regulating the lowered reference voltage at the reference node.