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US 2023/0410863 A1Published application
Memory device and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jun SHIN, Tae-Young OH
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Abstract
A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.
Claims20
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a control logic configured to:
- receive an active command which is split into a first portion and a second portion, the active command including a bank address and a row address for activating a word line corresponding to the bank address and the row address;
- and
- receive a column address strobe (CAS) command between the first portion and the second portion of the active command.
3 more elements
A memory system, comprising:
- a memory controller configured to generate a clock signal;
- and
- a memory device, including:
- a memory cell array having a plurality of memory cells;
- and
- a control logic configured to:
- receive the clock signal from the memory controller;
- receive an active command which is split into a first portion and a second portion, the active command including a bank address and a row address for activating a word line corresponding to the bank address and the row address;
- and
- receive a column address strobe (CAS) command between the first portion and the second portion of the active command.
7 more elements
Dependencies are inferred from the claim text.