In-memory computation circuit using static random access memory (sram) array segmentation

An in-memory computation circuit, comprising:

• a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column, said memory cells configured to store bits of weight data for an in-memory compute operation;
• a word line driver circuit for each row having an output connected to drive the word line of the row;
• a row controller circuit configured to simultaneously actuate only one word line per sub-array for the in-memory compute operation by applying pulses through the word line driver circuits to the word lines;
• and
• a plurality of global bit lines, where each global bit line is capacitively coupled to a plurality of local bit lines.