Semiconductor memory device, memory system, and method

A memory system comprising:

• a first device;
• and
• a semiconductor memory device including a first chip, a second chip, and a third chip, the third chip being connected to the first device, the third chip being connected to the first chip via a first channel and connected to the second chip via a second channel,
• wherein the third chip is configured to:
• receive a first command sequence to request status information from the first device, the first command sequence including at least a first address indicating the first chip,
• in accordance with receiving first command sequence, perform transfer of a second command sequence including the first address via the first channel and transfer of a third command sequence including a second address indicating the second chip via the second channel,
• transfer first read enable signals to the first channel and the second channel in parallel after a first time elapses from completion of the transfers of the second command sequence and the third command sequence, and acquire pieces of first status information in parallel via the first channel and the second channel, and
• output the first status information to the first device on the basis of a second read enable signal in a case where the second read enable signal is received from the first device.

A method of controlling a semiconductor device, the method comprising:

• receiving, from a first device, a first command sequence to request status information, the first command sequence including at least a first address indicating a first chip connected to the semiconductor device via a first channel;
• in accordance with receiving first command sequence, performing transfer of a second command sequence including the first address via the first channel and transfer of a third command sequence including a second address via a second channel, the second address indicating a second chip connected to the semiconductor device via the second channel;
• transferring first read enable signals to the first channel and the second channel in parallel after a first time elapses from completion of the transfers of the second command sequence and the third command sequence, and acquiring pieces of first status information in parallel via the first channel and the second channel;
• and
• outputting the first status information to the first device on the basis of a second read enable signal in a case where the second read enable signal is received from the first device.