Timing controller having mechanism for frame synchronization, display panel thereof, and display system thereof

A display panel comprising:

• a display comprising a pixel array for displaying images, and
• an integrated circuit coupled to the display and comprising:
• a timing controller to transmit a first tearing (TE) signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and
• a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal, wherein the timing controller further to transmit a third TE signal to an application processor and receive a third image frame from the application processor after the application processor receives the third TE signal, and
• the control circuit further to generate a third sync signal when the timing controller receives the third image frame, wherein when the application processor receives a fourth TE signal, the control circuit further to generate a fourth sync signal, and a first interval between the first sync signal and the second sync signal is different from a second interval between the third sync signal and the fourth sync signal.

A display system comprising:

• an electronic device comprising:
• a graphics control unit (GPU), and
• an application processor (AP) coupled to the GPU and configured to output a plurality of render images to a display panel, and
• the display panel comprising:
• a display, and
• an integrated circuit coupled to the display and comprising:
• a timing controller to transmit a first tearing (TE) signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and
• a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal, wherein the timing controller further to transmit a third TE signal to an application processor and receive a third image frame from the application processor after the application processor receives the third TE signal, and
• the control circuit further to generate a third sync signal when the timing controller receives the third image frame, wherein when the application processor receives a fourth TE signl, the control circuit further to generate a fourth sync signal, and a first interval between the first sync signal and the second sync signal is different from a second interval between the third sync signal and the fourth sync signal.