Method and apparatus for performing deconvolution processing on feature data by using convolution hardware

An electronic device, comprising:

• a dedicated convolution hardware, comprising a multiply-add array and an on-chip memory;
• at least one off-chip memory, storing instructions;
• and
• at least one processor,
• wherein, when the instructions are run by the processor, the electronic device is enabled to implement a method for performing deconvolution processing on a feature map, and the method comprising:
• reading the feature map and a deconvolution kernel into the on-chip memory, and performing zero-padding processing on the feature map;
• determining a plurality of convolution kernels based on the deconvolution kernel;
• removing a row and/or column of each convolution kernel in which all elements are invalid weights to obtain an optimized convolution kernel, and removing a corresponding row and/or column in a zero-padded feature map to obtain an optimized feature map corresponding to each optimized convolution kernel;
• performing convolution processing on each optimized convolution kernel and the corresponding optimized feature map by using the multiply-add array, to obtain a plurality of convolutional outputs;
• and
• performing interleaving synthesis processing on the plurality of convolutional outputs, to obtain an interleaving synthetic output, wherein the interleaving synthetic output comprises a deconvolutional output corresponding to the feature map and the deconvolution kernel.

A computer readable storage medium, storing computer program instructions, wherein

• when the computer program instructions are run by an electronic device, the electronic device is enabled to implement a method for performing deconvolution processing on a feature map;
• and
• the electronic device further comprises dedicated convolution hardware, the dedicated convolution hardware comprising a multiply-add array and an on-chip memory,
• wherein the method comprises:
• reading the feature map and a deconvolution kernel into the on-chip memory, and performing zero-padding processing on the feature map;
• determining a plurality of convolution kernels based on the deconvolution kernel;
• removing a row and/or column of each convolution kernel in which all elements are invalid weights to obtain an optimized convolution kernel, and removing a corresponding row and/or column in a zero-padded feature map to obtain an optimized feature map corresponding to each optimized convolution kernel;
• performing convolution processing on each optimized convolution kernel and the corresponding optimized feature map by using the multiply-add array, to obtain a plurality of convolutional outputs;
• and
• performing interleaving synthesis processing on the plurality of convolutional outputs, to obtain an interleaving synthetic output, wherein the interleaving synthetic output comprises a deconvolutional output corresponding to the feature map and the deconvolution kernel.