System and method for performing deformation and stress analysis modeling in a virtual fabrication environment

A computing device-implemented method for performing deformation and stress analysis modeling in a virtual fabrication environment, comprising:

• receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified deformation and stress analysis modeling step, the deformation and stress analysis modeling step indicating a point during the process sequence for deformation and stress analysis modeling to be performed;
• performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
• executing the process sequence up until the deformation and stress analysis modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and
• performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data;
• and
• outputting the result data generated from the deformation and stress analysis modeling step.

A system for performing deformation and stress analysis modeling in a virtual fabrication environment, comprising:

• at least one computing device equipped with one or more processors and configured to generate a virtual fabrication environment that includes a deformation and stress analysis modeling module, the deformation and stress analysis modeling module when executing:
• receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified deformation and stress analysis modeling step, the deformation and stress analysis modeling step indicating a point during the process sequence for deformation and stress analysis modeling to be performed;
• performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run:
• executing the process sequence up until the deformation and stress analysis modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, and
• performing the deformation and stress analysis modeling step, the deformation and stress analysis modeling step generating result data;
• and
• a display in communication with the at least one computing device, the display configured to display the result data from the deformation and stress analysis modeling step.