US 2023/0409748 A1Published application

Garbling enhancements

AssigneeVMware, Inc.

InventorAvishay YANAI

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Abstract

The disclosure provides an approach for data security. Embodiments include determining, by one or more garbling components running on one or more processing devices, first labels Ka0 and Ka1 representing values of 0 and 1 for a first input wire a of a gate g in a circuit, second labels Kb0 and Kb1 representing the values of 0 and 1 for a second input wire b of the gate g, and third labels Kc0 and Kc1 representing the values of 0 and 1 for an output wire c of the gate g. Embodiments include defining, by the one or more garbling components, four interpolation points based on Ka0, Ka1, Kb0, Kb1, Kc0, and Kc1 and determining, by the garbling component, using polynomial interpolation based on the four interpolation points, a polynomial Pg representing a garbled gate corresponding to gate g.

Claims20

Dependent claims

A method of data security, comprising:

determining, by one or more garbling components running on one or more processing devices:
first labels Ka0 and Ka1 representing values of 0 and 1 for a first input wire a of a gate g in a circuit;
second labels Kb0 and Kb1 representing the values of 0 and 1 for a second input wire b of the gate g;
and
third labels Kc0 and Kc1 representing the values of 0 and 1 for an output wire c of the gate g;
defining, by the one or more garbling components, four interpolation points based on Ka0, Ka1, Kb0, Kb1, Kc0, and Kc1;
determining, by the garbling component, using polynomial interpolation based on the four interpolation points, a polynomial Pg representing a garbled gate corresponding to gate g;
sending, by the one or more garbling components, to an evaluator component running on one or more additional processing devices:
the polynomial Pg;
and
a map indicating that Kc0 corresponds to 0 and that Kc1 corresponds to 1;
obtaining, by the evaluator component, input labels Ka and Kb for the first input wire a and the second input wire b, wherein at least one of Ka or Kb corresponds to a private input value that is not provided to the evaluator component;
evaluating, by the evaluator component, the polynomial Pg using Ka and Kb to determine an output label Kc for the output wire c;
and
determining, by the evaluator component, an output bit yc based on the output label Kc and the map.

12 more elements

A system for data security, the system comprising:

at least one memory;
and
at least one processor coupled to the at least one memory, the at least one processor and the at least one memory configured to:
determine, by one or more garbling components running on one or more processing devices:
first labels Ka0 and Ka1 representing values of 0 and 1 for a first input wire a of a gate g in a circuit;
second labels Kb0 and Kb1 representing the values of 0 and 1 for a second input wire b of the gate g;
and
third labels Kc0 and Kc1 representing the values of 0 and 1 for an output wire c of the gate g;
define, by the one or more garbling components, four interpolation points based on Ka0, Ka1, Kb0, Kb1, Kc0, and Kc1;
determine, by the garbling component, using polynomial interpolation based on the four interpolation points, a polynomial Pg representing a garbled gate corresponding to gate g;
send, by the one or more garbling components, to an evaluator component running on one or more additional processing devices:
the polynomial Pg;
and
a map indicating that Kc0 corresponds to 0 and that Kc1 corresponds to 1;
obtain, by the evaluator component, input labels Ka and Kb for the first input wire a and the second input wire b, wherein at least one of Ka or Kb corresponds to a private input value that is not provided to the evaluator component;
evaluate, by the evaluator component, the polynomial Pg using Ka and Kb to determine an output label Kc for the output wire c;
and
determine, by the evaluator component, an output bit yc based on the output label Kc and the map.

15 more elements

A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to:

determine, by one or more garbling components running on one or more processing devices:
first labels Ka0 and Ka1 representing values of 0 and 1 for a first input wire a of a gate g in a circuit;
second labels Kb0 and Kb1 representing the values of 0 and 1 for a second input wire b of the gate g;
and
third labels Kc0 and Kc1 representing the values of 0 and 1 for an output wire c of the gate g;
define, by the one or more garbling components, four interpolation points based on Ka0, Ka1, Kb0, Kb1, Kc0, and Kc1;
determine, by the garbling component, using polynomial interpolation based on the four interpolation points, a polynomial Pg representing a garbled gate corresponding to gate g;
send, by the one or more garbling components, to an evaluator component running on one or more additional processing devices:
the polynomial Pg;
and
a map indicating that Kc0 corresponds to 0 and that Kc1 corresponds to 1;
obtain, by the evaluator component, input labels Ka and Kb for the first input wire a and the second input wire b, wherein at least one of Ka or Kb corresponds to a private input value that is not provided to the evaluator component;
evaluate, by the evaluator component, the polynomial Pg using Ka and Kb to determine an output label Kc for the output wire c;
and
determine, by the evaluator component, an output bit yc based on the output label Kc and the map.

12 more elements

Dependencies are inferred from the claim text.