Protocol including timing calibration between memory request and data transfer

An integrated circuit (IC) memory controller to control the operation of an IC memory device having a memory array, the IC memory controller comprising:

• a command interface to transmit, to the IC memory device, a read command and a calibration command, wherein the calibration command specifies a calibration operation, to be performed by the IC memory device, in the intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to the read command;
• a data interface to receive the data;
• and
• a transmitter to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.

A method of operation in an integrated circuit (IC) memory controller, the method comprising:

• transmitting, via a command interface, a read command and a calibration command to an IC memory device, wherein the calibration command specifies a calibration operation to be performed by the IC memory device in the intervening time between receipt of the read command and prior to outputting data accessed in response to the read command;
• receiving the data via a data interface;
• and
• transmitting a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.

An integrated circuit (IC) memory controller to control the operation of an IC memory device, the IC memory controller comprising:

• command interface circuitry to transmit command information to the IC memory device, wherein the command information specifies:
• (i) a read operation in which data is accessed from the memory array, and
• (ii) a calibration operation to be performed by the IC memory device in the intervening time between receiving the command information and outputting the data accessed from the memory array;
• and
• data interface circuitry to receive the data;
• transmit circuitry to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.