Memory device supporting a high-efficient input/output interface and a memory system including the memory device

An operating method of memory system in two different operating modes, the method comprising:

• transmitting a command/address signal from a memory controller to a memory device, the command/address signal having one of two different voltage levels,
• transmitting a data input/output signal from the memory controller to the memory device, the data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first operating mode and the data input/output signal having one of two different voltage levels during a second operating mode;
• sampling, by the memory device, the received command/the address signal in a non-return to zero (NRZ) mode;
• and
• sampling, by the memory device, the received data input/output signal in a pulse amplitude modulation (PAM)-N mode during the first operating mode and in the NRZ mode during the second operating mode respectively.