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US 2023/0409493 A1Published application
Reducing performance degradation from negligent or malicious device attacks
AssigneeIntel Corporation
InventorsRupin Vakharwala, Garrett Drown
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Abstract
Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to optimizing memory access and minimizing performance degradation due to faulty or malicious devices attempting to access improper memory locations. Faulty/malicious devices' memory accesses are quickly blocked reducing performance degradation due to the avoidance of costly memory lookups and fault generation/processing. Other embodiments may be described and/or claimed.
Claims20
An apparatus comprising:
- an IO memory management unit (IOMMU), the IOMMU to receive a memory transaction request to access a system memory from a requesting device, the memory transaction request including a device address;
- the IOMMU to process the memory transaction request including to perform a translation of the device address to a physical memory address of the system memory;
- wherein to process the memory transaction request the IOMMU to access an address mapping table, the address mapping table containing a table entry corresponding to the requesting device;
- the table entry comprising:
- a blocking identifier corresponding to the requesting device indicating whether the memory transaction from the requesting device is to be rejected.
2 more elements
A method comprising:
- receiving a memory transaction from a requesting device, the memory transaction including a device address;
- accessing a memory mapping table to remap the device address to a physical address;
- identifying a table entry in the memory mapping table corresponding to the requesting device, the table entry comprising a blocking identifier;
- and
- rejecting the memory transaction from the requesting device if the blocking identifier in the table entry indicates the memory transaction is to be rejected.
2 more elements
A system comprising:
- a system memory;
- an entity to request a memory transaction, the memory transaction including a device address;
- and
- an IO memory management unit (IOMMU) coupled to the system memory and the entity;
- the IOMMU to receive the memory transaction request;
- the IOMMU to process the memory transaction request including to perform a translation of the device address to a physical memory address of the system memory;
- wherein to process the memory transaction request, the IOMMU to access an address mapping table, the address mapping table containing a table entry corresponding to the entity;
- the table entry comprising:
- blocking information corresponding to the entity indicating whether the memory transaction from the entity is to be rejected.
6 more elements
Dependencies are inferred from the claim text.