Instructions and support for calculating prefix sums

A method comprising:

• decoding an instance of a single instruction, the single instruction including fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
• perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
• store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand;
• and
• executing the decoded instruction according to the opcode.

A method comprising:

• translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture, the single instruction including fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
• perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
• store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand;
• and
• decoding the one or more instructions of the second instruction set architecture;
• executing the decoded one or more instructions of the second instruction set architecture instruction according to the opcode of the single instruction of the first instruction set architecture.

A system comprising:

• memory to store an instance of a single instruction;
• and
• a processor core comprising:
• decoder circuitry to decode an instance of the single instruction, the single instruction to include fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least:
• perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and
• store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand;
• and
• execution circuitry configured to execute the decoded instruction according to the opcode.