Devices transferring cache lines, including metadata on external links
AssigneeAmpere Computing LLC
InventorRobert James Safranek
Life of this patent
Estimating the term…
Loading patent…
AssigneeAmpere Computing LLC
InventorRobert James Safranek
Estimating the term…
In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.
A device comprising:
A method, in a device, of a conversion circuit providing a flow control unit (FLIT) to a link interface circuit of the device, the method comprising:
A device comprising:
Dependencies are inferred from the claim text.