One-time programmable memory controller, related processing system, integrated circuit and method

A method for operating a processing system, the method comprising:

• switching-on the processing system;
• in response to switching-on the processing system, asserting, by a power supply monitoring circuit of the processing system, a preload start signal and setting a preload enable signal in order to preload first configuration data from a first memory slot to a first shadow-register and second configuration data from a second memory slot to a second shadow-register;
• in response to a preload end signal, transferring the first configuration data from the first shadow-register to a first resource and the second configuration data from the second shadow-register to a second resource;
• sending, by a digital processing circuit of the processing system, a request to a power management circuit in order to assert a low-power control signal thereby disabling a first supply voltage and switching-off a first sub-circuit;
• in response to an event signal, de-asserting, by the power management circuit, the low-power control signal thereby enabling the first supply voltage and switching-on the first sub-circuit;
• and
• in response to switching-on the first sub-circuit, asserting the preload start signal via the power supply monitoring circuit and setting the preload enable signal in order to preload the first configuration data from the first memory slot to the first shadow-register and disable the preloading of the second configuration data from the second memory slot to the second shadow-register and, in response to the preload end signal, transferring the first configuration data from the first shadow-register to the first resource and inhibiting the transfer of the second configuration data from the second shadow-register to the second resource.

A One-Time Programmable (OTP) memory controller comprising:

• a data register;
• a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area;
• a communication interface configured to receive a read request requesting the data of a given memory slot;
• and
• a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase,
• wherein, in response to the preload start signal, the control circuit is configured to perform the preload phase by:
• determining a mapping between the given number K of shadow-registers and the given number N of memory slots,
• determining, for each of the shadow-registers, whether the respective shadow-register is preloadable as a function of the shadow-register preload enable signal,
• in response to determining that a shadow-register is preloadable, transferring data from the memory slot mapped to the shadow-register to the respective shadow-register, and
• once the shadow-register is preloaded based on the shadow-register preload enable signal, asserting a preload end signal and start the data-read phase.