Multiplexer for sdfq having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same

A semiconductor device, comprising:

• a cell region including first, second, third and fourth active regions that extend in a first direction and correspondingly having components of first transistors, second transistors, third transistors and fourth transistors formed therein;
• the first active region and the second active region having a first height with respect to a second direction, the second direction being perpendicular to the first direction;
• the third active region and the fourth active region having a second height with respect to the second direction, the second height being smaller than the first height;
• and
• the transistors of the cell region being arranged to function as a scan insertion D flip flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF);
• the multiplexer including:
• corresponding ones of the first transistors and the second transistors as data transistors for selecting a data input signal;
• and
• corresponding ones of the third transistors and the fourth transistors as scan transistors for selecting a scan input signal.

A method of forming a semiconductor device, the method comprising:

• forming active regions (ARs) in a substrate, including doping corresponding areas of the substrate, resulting in:
• first, second, third and fourth active regions extending in a first direction;
• each of the first and second active regions having a first height with respect to a second direction, the second direction being perpendicular to the first direction;
• and
• each of the third and fourth active regions having a second height with respect to the second direction, the second height being smaller than the first height;
• forming source/drain (S/D) regions resulting in channel regions between corresponding S/D regions;
• and
• forming gate lines;
• the forming active regions, the forming S/D regions and the forming gate lines further resulting in transistors which are configured to define a scan insertion D flip flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF), the multiplexer including:
• data transistors for selecting a data input signal;
• and
• scan transistors for selecting a scan input signal.