US 2023/0408571 A1 · METHOD FOR REDUCTION OF SIC MOSFET GATE VOLTAGE GLITCHES

Abstract

Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.

Claims22

Dependent claims

An automated test equipment (ATE) for testing a device under test (DUT) comprising a first transistor having a gate terminal and a source terminal, the ATE comprises:

a first control circuit configured to drive the first transistor;
a second control circuit configured to drive a second transistor having a gate terminal and a source terminal, the second transistor coupled to the first transistor in an inverter configuration, each control circuit comprises:
a gate line configured to be connected to the gate terminal of a corresponding transistor;
a source line configured to be connected to the source terminal of a corresponding transistor;
a first circuit path and a second circuit path connected in parallel between the gate line and the source line, wherein
the first circuit path is configured to switchably bias the gate line with a positive voltage relative to the source line,
the second circuit path is configured to switchably bias the gate line with a negative voltage relative to the source line and comprises a programmable resistance.

4 more elements

A method for driving a first power transistor and a second power transistor coupled in an inverter configuration using a first control circuit and a second control circuit, each control circuit comprising a first circuit path and a second circuit path connected in parallel, the method comprising:

driving the first power transistor with the first control circuit by:
with the first circuit path, switchably coupling a gate terminal of the first power transistor with a first power source having a positive voltage relative to a source terminal of the first power transistor;
with the second circuit path, switchably coupling the gate terminal of the first power transistor with a second power source having a negative voltage relative to the source terminal of the first power transistor via a first programmable resistance;
and driving the second power transistor with the second control circuit by:
with the first circuit path, switchably coupling a gate terminal of the second power transistor with a third power source having a positive voltage relative to a source terminal of the second power transistor;
with the second circuit path, switchably coupling the gate terminal of the second power transistor with a fourth power source having a negative voltage relative to the source terminal of the second power transistor via a second programmable resistance.

3 more elements

Dependencies are inferred from the claim text.

Method for reduction of sic mosfet gate voltage glitches

Life of this patent

Method for reduction of sic mosfet gate voltage glitches

Life of this patent

Abstract

Claims22