Semiconductor devices having parallel-to-serial converters therein

A semiconductor device, comprising:

• a first logic circuit connected between a first input node receiving a first data input signal and an output node, and configured to output the first data input signal to the output node at a rising edge of a first clock signal having a phase difference of 90 degrees from the first data input signal;
• a second logic circuit connected between a second input node receiving a second data input signal and the output node, and configured to output the second data input signal to the output node at a rising edge of a second clock signal having a phase difference of 90 degrees from the second data input signal;
• a third logic circuit connected between a third input node receiving a third data input signal and the output node, and configured to output the third data input signal to the output node at a rising edge of a third clock signal that is 180 degrees out of phase relative to the first clock signal;
• and
• a fourth logic circuit connected between a fourth input node receiving a fourth data input signal and the output node, and configured to output the fourth data input signal to the output node at a rising edge of a fourth clock signal that is 180 degrees out of phase relative to the second clock signal.

A semiconductor device, comprising:

• a clock buffer configured to output a plurality of clock signals having different phases;
• and
• a selection circuit including a plurality of logic circuits selecting one of a plurality of data input signals and outputting a selected data input signal as a data output signal, each of the plurality of logic circuits receiving the plurality of clock signals and one of the plurality of data input signals,
• wherein each of the plurality of logic circuits outputs the one of the plurality of data input signals as the data output signal at a point in which at which a value of a pair of clock signals among the plurality of clock signals changes.