Integrated circuit structures including backside vias

An integrated circuit (IC) structure, comprising:

• a device layer;
• a first metallization layer over the device layer;
• a second metallization layer under the device layer;
• and
• a conductive via through the device layer, wherein:
• the device layer includes:
• a first fin having a first semiconductor material and a first conductive material;
• a second fin parallel to the first fin, and having a second semiconductor material and a second conductive material, the second semiconductor material being different from the first semiconductor material;
• and
• a first portion of an insulator separating the first fin and the second fin,
• the first metallization layer includes a first conductive pathway in conductive contact with at least one of the first fin and the second fin,
• the second metallization layer includes:
• a second conductive pathway in direct contact with at least one of the first fin and the second fin;
• and
• a second portion of the insulator that is coplanar with the second conductive pathway,
• the conductive via is perpendicular to the first fin and the second fin,
• the conductive via is in direct contact with the first conductive material and the second conductive material, and
• the conductive via is in conductive contact with the first conductive pathway and the second conductive pathway.

A fin-based IC structure, comprising:

• a first fin including an N-type body region, two P-type epitaxial regions over the N-type body region, and a first gate electrode between the two P-type epitaxial regions;
• a second fin parallel to the first fin, the second fin including a P-type body region, two N-type epitaxial regions over the P-type body region, and a second gate electrode between the two N-type epitaxial regions;
• a first interconnect over the first fin and the second fin electrically coupled to at least one of a frontside metallization stack, the first gate electrode, and the second gate electrode;
• a second interconnect under the first fin and the second fin electrically coupled to a backside metallization stack;
• and
• a backside conductive via perpendicular to the first fin and the second fin and in contact with the first interconnect and the second interconnect.

An IC, comprising:

• a driver circuitry;
• an electrostatic discharge protection (ESDP) circuitry;
• and
• an input/output (IO) pad electrically coupled to the ESDP circuitry, wherein:
• the ESDP circuitry comprises:
• a first fin structure and a second fin structure in a device layer between a frontside metallization stack and a backside metallization stack;
• and
• a conductive via in the device layer perpendicular to the first fin structure and the second fin structure,
• the IO pad is in the backside metallization stack,
• the driver circuitry is coupled to an IO signal pathway by the frontside metallization stack, and
• the conductive via in the ESDP circuitry electrically couples the IO signal pathway in the frontside metallization stack with the IO pad in the backside metallization stack.