Electrostatic discharge protection for high speed transceiver interface

An electrical overstress (EOS) protection device comprising:

• a p-type substrate;
• a plurality of wells including a first p-type well (PW), a second PW, an n-type well (NW), a first deep n-type well (DNW) electrically isolating the first PW from the p-type substrate, and a second DNW electrically isolating the second PW from the p-type substrate;
• a plurality of active regions including a first n-type active (N+) region formed in the first PW and connected to a cathode terminal, a second N+ region formed in the second PW, a first p-type active (P+) region formed in the NW and connected to the second N+ region in metallization, and a second P+ region formed in the second PW and connected to an anode terminal,
• wherein the first P+ region, the NW, and first PW form a first PNP bipolar transistor, and the first N+ region, the first PW, and the NW form a first NPN bipolar transistor that is cross-coupled with the first PNP bipolar transistor to form a first silicon controlled rectifier (SCR), wherein the second N+ region, the second PW, and the second DNW form a second NPN bipolar transistor, and wherein the first P+ region, the NW, and the p-type substrate form a second PNP bipolar transistor, wherein two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the first SCR and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

A protection device, comprising:

• an anode terminal and a cathode terminal;
• a first silicon controlled rectifier;
• an NPN bipolar transistor and a PNP bipolar transistor, the NPN bipolar transistor and the PNP bipolar transistor are configured to provide a second silicon controlled rectifier in parallel to the silicon controlled rectifier,
• wherein two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the PNP bipolar transistor.