Integrated standard cell structure

An integrated circuit structure, comprising:

• a fin structure including a first portion having a first width, a second portion having a second width, and a third portion having a third width, the fin structure protruding from a semiconductor substrate, wherein the third portion extends from the first portion to the second portion, and wherein the second width differs from the first width;
• a first transistor in a first standard cell, wherein the first transistor includes a first metal gate stack engaged with the first portion;
• a second transistor in a second standard cell, wherein the second transistor includes a second metal gate stack engaged with the second portion;
• a dielectric gate disposed between the first metal gate stack and the second metal gate stack;
• a third metal gate stack disposed between the dielectric gate and the second metal gate stack, wherein the third metal gate stack is inactive;
• and
• a filler cell sandwiched between the first standard cell and the second standard cell, wherein boundaries of the filler cell are defined by the dielectric gate and the third metal gate stack, and wherein the third fin extends across a width of the filler cell.

A method, comprising:

• forming a fin structure including a first portion, a second portion, and a third portion over a substrate, wherein the third portion extends continuously in a first direction between the first portion and the second portion, and wherein the second portion and the third portion differ in a width measured along the second direction perpendicular to the first direction;
• forming a first dummy gate structure, a second dummy gate structure, a third dummy gate structure, and a fourth dummy gate structure each oriented lengthwise in the second direction, wherein the first dummy gate structure and the second dummy gate structure engage with the first portion and the second portion, respectively, and wherein the third dummy gate structure and the fourth dummy gate structure are disposed between the first dummy gate structure and the second dummy gate structure;
• replacing the third dummy gate structure with a dielectric gate;
• removing the first dummy gate structure, the second dummy gate structure, and the fourth dummy gate structure to form a first trench, a second trench, and a third trench, respectively;
• and
• forming a first metal gate stack, a second metal gate stack, and a third metal gate stack in the first trench, the second trench, and the third trench, respectively, wherein:
• the first metal gate stack engages with the first portion to form a first transistor in a first standard (STD) cell,
• the second metal gate stack engages with the second portion to form a first transistor in a second STD cell,
• the third metal gate stack defines a first boundary of a filler cell sandwiched between the first STD cell and the second STD cell,
• the dielectric gate defines a second boundary of the filler cell, and
• the third portion spans a width of the filler cell.