Forming Structures In Empty Regions On Wafers With Dual Seal Ring Structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShan-Yu Huang, Yilun Chen, Huang-Sheng Lin
Life of this patent
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Abstract
A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.
Claims20
A device, comprising:
- a first die that includes a plurality of first transistors;
- a first seal ring that surrounds the first die in a top view;
- a second die that includes a plurality of second transistors;
- a second seal ring that surrounds the second die in the top view;
- a plurality of conductive elements that extend into both the first die and the second die in the top view, wherein the conductive elements electrically interconnect the first die with the second die;
- and
- a third seal ring that surrounds, in the top view, the first die, the second die, and the conductive elements.
A wafer-level structure, comprising:
- a plurality of integrated circuit (IC) dies, wherein each of the IC dies contains electrical circuitry;
- a plurality of first seal ring structures that each surrounds a respective one of the IC dies in a top view;
- a second seal ring structure that surrounds a subset of the IC dies in the top view, wherein the first seal ring structures surrounding each of the IC dies are also surrounded by the second seal ring structure in the top view;
- and
- a plurality of conductive elements surrounded by the second seal ring structure in the top view, wherein the conductive elements electrically couple the subset of IC dies with one another, wherein at least a first subset of the conductive elements each extend in a first horizontal direction in a top view, and wherein at least a second subset of the conductive elements each extend diagonally with respect to the first horizontal direction in the top view.
A method, comprising:
- forming active layers of a first integrated circuit (IC) die and a second IC die in a substrate;
- forming interconnect structures of the first IC die and the second IC die over the active layers, wherein the interconnect structures includes a first seal ring, a second seal ring, and a third seal ring, wherein the first seal ring and the second seal ring respectively encircle the first IC die and the second IC die in a top view, wherein the third seal ring encircles the first IC die, the second IC die, the first seal ring, and the second seal ring in the top view, and wherein the interconnect structures further includes a plurality of conductive elements that extend into the first IC die and the second IC die and electrically couple the first IC die and the second IC die together;
- and
- forming one or more test structures, one or more dummy structures, one or more process monitor patterns, one or more alignment marks, or one or more overlay marks in a region outside the first seal ring and the second seal ring but still encircled by the third seal ring.
Dependencies are inferred from the claim text.