US 2023/0402098 A1 · 3D MEMORY DEVICES AND STRUCTURES WITH CONTROL CIRCUITS

Abstract

A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Claims20

Dependent claims

A semiconductor device, the device comprising:

a first level comprising a plurality of first memory arrays,
wherein said first level comprises a plurality of first transistors and a plurality of first metal layers;
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays;
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes, and
wherein said third level comprises a plurality of decoder circuits.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/239,117Filed 28 Aug 2023

Priority

10 Oct 2016

Published

14 Dec 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification49 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 29/1201
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising I/O circuitry
G11C 11/4087
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits

Family

Application62/406,376Us provisional application · filed 10 Oct 2016

Application62/440,720Us provisional application · filed 30 Dec 2016

Application62/471,963Us provisional application · filed 16 Mar 2017

Application62/517,152Us provisional application · filed 8 Jun 2017

Application16/337,665Continuation in part · filed 28 Mar 2019

Application17/214,883Continuation in part · filed 28 Mar 2021

Application17/372,476Continuation in part · filed 11 Jul 2021

Application17/485,504Continuation in part · filed 27 Sep 2021

Application17/567,049Continuation in part · filed 31 Dec 2021

Application17/712,875Continuation in part · filed 4 Apr 2022

Application17/949,988Continuation in part · filed 21 Sep 2022