US 2023/0402087 A1 · SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT

Abstract

A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction. The third sense amplifier belongs to a second sense amplifier group. The first and second sense amplifier groups are adjacent to each other and are arranged in the first direction.

Claims20

Dependent claims

A memory device comprising:

a first memory cell provided above a substrate;
a first bit line extending in a first direction, the first bit line electrically coupled to the first memory cell;
a first sense amplifier configured to sense a voltage of the first bit line;
a second memory cell provided above the substrate;
a second bit line adjacent to the first bit line and extending in the first direction, the second bit line electrically coupled to the second memory cell;
a second sense amplifier configured to sense a voltage of the second bit line;
a third memory cell provided above the substrate;
a third bit line not adjacent to the second bit line:
extending in the first direction, the third bit line electrically coupled to the third memory cell;
and
a third sense amplifier configured to sense a voltage of the third bit line, wherein:
the first sense amplifier and the second sense amplifier belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting to the first direction,
the third sense amplifier belongs to a second sense amplifier group, and
the first sense amplifier group and the second sense amplifier group are adjacent to each other and arranged in the first direction.

11 more elements

A memory device comprising:

a first bit line extending in a first direction;
a second bit line adjacent to the first bit line, the second bit line extending in the first direction;
a third bit line extending in the first direction;
a fourth bit line adjacent to the third bit line, the fourth bit line extending in the first direction;
a first sense amplifier group including:
a first sense amplifier configured to sense a voltage of the first bit line, and
a second sense amplifier configured to sense a voltage of the second bit line, the first sense amplifier and the second sense amplifier arranged in a second direction intersecting the first direction;
and
a second sense amplifier group disposed adjacent to the first sense amplifier group in the first direction, the second sense amplifier group including:
a third sense amplifier configured to sense a voltage of the third bit line, and
a fourth sense amplifier configured to sense a voltage of the fourth bit line, the third sense amplifier and the fourth sense amplifier arranged in the second direction.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having memory chip bonded to a cmos chip including a peripheral circuit

Life of this patent

Semiconductor memory device having memory chip bonded to a cmos chip including a peripheral circuit

Life of this patent

Abstract

Claims20