Semiconductor device

A semiconductor device comprising:

• a bit line;
• a first memory cell that is connected to the bit line and includes a first storage element of a variable resistance type;
• a second memory cell that is connected to the bit line, includes a second storage element having same electrical characteristics as the first storage element, and is used as a One Time Programmable (OTP) cell;
• a clamp element configured to apply a fixed potential to the bit line at a time of a readout operation;
• a reference current source configured to generate a reference current;
• a sense amplifier configured to apply the fixed potential to the second memory cell at the time of the readout operation to detect, by using the reference current, a magnitude of a cell current flowing through the bit line;
• a first offset current source that is activated at a time of the readout operation for the second memory cell, and is configured to generate, at a time of being activated, a first offset current to be subtracted from the cell current;
• a second offset current source that is activated at a time of the readout operation for the second memory cell, and is configured to generate, at a time of being activated, a second offset current to be added to the cell current;
• and
• a control circuit configured to, at the time of the readout operation for the second memory cell, activate either one of the first offset current source and the second offset current source, and variably control a value of the first offset current or a value of the second offset current,
• wherein, at the time of the readout operation for the second memory cell, the sense amplifier detects a magnitude relationship between the reference current and a readout current obtained by subtracting the first offset current from the cell current, or detects a magnitude relationship between the cell current or a readout current obtained by adding the second offset current to the cell current.

A semiconductor device composed of one semiconductor chip, comprising:

• a processor:
• a nonvolatile memory;
• and
• a bus configured to connect the processor and the nonvolatile memory to each other,
• wherein the nonvolatile memory comprises:
• a bit line;
• a first memory cell that is connected to the bit line and includes a first storage element of a variable resistance type;
• a second memory cell that is connected to the bit line, includes a second storage element having same electrical characteristics as the first storage element, and is used as a One Time Programmable (OTP) cell;
• a clamp element configured to apply a fixed potential to the bit line at a time of a readout operation;
• a reference current source configured to generate a reference current;
• a sense amplifier configured to apply the fixed potential to the first memory cell or the second memory cell at the time of the readout operation to detect, by using the reference current, a magnitude of a cell current flowing through the bit line;
• and
• an offset current source that is activated at a time of the readout operation for the second memory cell, and is configured to generate, at a time of being activated, an offset current to be subtracted from the cell current, and
• wherein, at the time of the readout operation for the second memory cell, the sense amplifier detects a magnitude relationship between the reference current and a readout current obtained by subtracting the offset current from the cell current.

A semiconductor device comprising:

• a first word line and a second word line;
• a bit line;
• a first memory cell that is connected to the first word line and the bit line and includes a first storage element of a variable resistance type;
• a second memory cell that is connected to the second word line and the bit line, includes a second storage element having same electrical characteristics as the first storage element, and is used as a One Time Programmable (OTP) cell;
• a clamp element configured to apply a fixed potential to the bit line at a time of a readout operation;
• a reference current source configured to generate a reference current;
• and
• a sense amplifier configured to apply the fixed potential to the first memory cell or the second memory cell at the time of the readout operation to detect, by using the reference current, a magnitude of a cell current flowing through the bit line,
• wherein the first memory cell includes a first selection transistor configured to form a current path of the first storage element and the bit line at a time when the first word line is activated,
• wherein the second memory cell includes a second selection transistor configured to form a current path of the second storage element and the bit line at a time when the second word line is activated,
• wherein the first selection transistor is composed of i pieces of transistor elements, where i is an integer of 1 or more,
• wherein the second selection transistor is composed of j pieces of transistor elements, where j is an integer larger than i,
• wherein the second word line is composed of a plurality of divided word lines which are individually activated,
• wherein i pieces among the j pieces of transistor elements are controlled to be ON/OFF by any one of the plurality of divided word lines, and
• wherein j−i pieces among the j pieces of transistor elements are controlled to be ON/OFF by any other one of the plurality of divided word lines.