Apparatus and method for reading data based on a program status of a non-volatile memory device

A memory system comprising:

• a controller configured to transfer a read command and an address associated with the read command to a memory device, receive data associated with the read command from the memory device, and perform an error correction based on hard decision data and soft decision data associated with the data after an error is detected in the data, wherein:
• the memory device is configured to consecutively read the hard decision data and the soft decision data from a first memory cell corresponding to the address in response to the read command, and
• the memory device comprises:
• a memory group comprising a plurality of memory cells;
• a control circuitry configured to consecutively read the hard decision data and the soft decision data from the first memory cell among the plurality of memory cells;
• and
• a page buffer circuit coupled to the first memory cell via a bit line, the page buffer circuit comprising a plurality of data latches configured to store the hard decision data and the soft decision data and at least one cache latch configured to store one of the hard decision data and the soft decision data which are transferred from the plurality of data latches.

A method for operating a memory system, comprising:

• consecutively reading a first hard decision data entry and a first soft decision data entry from a first memory cell in response to a first read command and a first address, and storing the first hard decision data entry and the first soft decision data entry in a first data latch and a second data latch;
• transferring the first hard decision data entry and the first soft decision data entry from the first data latch and the second data latch to at least one cache latch;
• outputting the first hard decision data entry or the first soft decision data entry stored in the at least one cache latch via a channel coupled to a memory die;
• and
• consecutively reading a second hard decision data entry and a second soft decision data entry from a second memory cell, coupled to the first memory cell via a bit line, in response to a second read command and a second address while the first hard decision data entry and the first soft decision data entry are output from the first data latch and the second data latch via the channel.