Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods

A memory system, comprising:

• a memory column access circuit;
• and
• a memory array, comprising:
• a first metal layer;
• a second metal layer different from the first metal layer, the second metal layer comprising a plurality of flying bit lines each coupled to the memory column access circuit;
• a first memory sub-bank, comprising:
• a plurality of first memory row circuits each comprising a plurality of first memory bit cell circuits each located in a respective first memory column circuit of a plurality of first memory column circuits;
• and
• a plurality of first bit lines disposed in the first metal layer and each coupled to a first memory column circuit of the plurality of first memory column circuits, and the memory column access circuit;
• and
• a second memory sub-bank, comprising:
• a plurality of second memory row circuits each comprising a plurality of second memory bit cell circuits each located in a respective second memory column circuit of a plurality of second memory column circuits;
• and
• a plurality of second bit lines each disposed in the first metal layer and each coupled to a second memory column circuit of the plurality of second memory column circuits;
• and
• a first jumper row circuit comprising a plurality of first jumper cell circuits each coupled to a second bit line of the plurality of second bit lines in a second memory column circuit of the plurality of second memory column circuits in the first metal layer, and a first flying bit line of the plurality of first flying bit lines in the second metal layer.