Memory apparatus embedded with computing function and operation method thereof

A memory apparatus embedded with a computing function, comprising:

• a memory array comprising a plurality of block groups, wherein each of the plurality of the block groups comprises a plurality of memory blocks;
• a plurality of data flow controllers respectively coupled to the plurality of the block groups and configured to respectively select transmission paths of data of the plurality of the memory blocks in the plurality of the block groups according to a plurality of data flow control signals;
• a plurality of computation circuits respectively coupled to the plurality of the data flow controllers and configured to compute a first data from the corresponding memory block in a computation mode;
• a data bus coupled to the plurality of the data flow controllers and transmitting a second data with the corresponding memory block in a normal mode;
• and
• a control logic circuit coupled to the memory array, the plurality of the data flow controllers, and the plurality of the computation circuits, the control logic circuit configured to determine whether the memory apparatus is currently in the normal mode or the computation mode, and accordingly provide the plurality of the data flow controllers with the plurality of the data flow control signals,
• wherein each of the plurality of the data flow controllers transmits the first data from the corresponding memory block to the corresponding computation circuit according to a corresponding data flow control signal to compute the first data, wherein the control logic circuit comprises:
• a mode register configured to store a mode setting code,
• wherein the control logic circuit is configured to determine whether the memory apparatus is currently in the normal mode or the computation mode according to the mode setting code and accordingly provide the plurality of the data flow control signals.