US 2023/0315386 A1 · ROUNDING HEXADECIMAL FLOATING POINT NUMBERS USING BINARY INCREMENTORS

Abstract

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

Claims20

Dependent claims

A method of rounding hexadecimal floating point numbers using binary incrementors, the method comprising:

incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
incrementing, by a second incrementor, a second subset of bits of the operand;
generating an intermediate result based on a carryout of the second incrementor;
and
generating an incremented result based on a carryout of the first incrementor and one or more of:
a first bit of the intermediate result or the carryout of the second incrementor.

3 more elements

A chip for rounding hexadecimal floating point numbers using binary incrementors, comprising:

a first incrementor;
a second incrementor;
and
wherein the chip is configured to perform steps comprising:
incrementing, by the first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
incrementing, by the second incrementor, a second subset of bits of the operand;
generating an intermediate result based on a carryout of the second incrementor;
and
generating an incremented result based on a carryout of the first incrementor and one or more of:
a first bit of the intermediate result or the carryout of the second incrementor.

7 more elements

An apparatus for rounding hexadecimal floating point numbers using binary incrementors, the apparatus comprising a chip comprising:

a first incrementor;
a second incrementor;
and
wherein the chip is configured to perform steps comprising:
incrementing, by the first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
incrementing, by the second incrementor, a second subset of bits of the operand;
generating an intermediate result based on a carryout of the second incrementor;
and
generating an incremented result based on a carryout of the first incrementor and one or more of:
a first bit of the intermediate result or the carryout of the second incrementor.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/705,036Filed 25 Mar 2022

Published

5 Oct 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 7/49947
Significance control: rounding
G06F 7/4836
Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or…:…
G06F 7/74
Methods or arrangements for processing data by operating upon the order or content of the data handled: selecting or encoding within a word the…
G06F 2207/3844
Less usual number representations: hexadecimal

Rounding hexadecimal floating point numbers using binary incrementors

Life of this patent

Rounding hexadecimal floating point numbers using binary incrementors

Life of this patent

Abstract

Claims20