Adaptive integrated programmable device platform

A System-on-Chip, comprising:

• a data processing engine array comprising a plurality of data processing engines organized in a grid;
• wherein the plurality of data processing engines are partitioned into at least a first partition and a second partition;
• wherein the first partition includes one or more first data processing engines of the plurality of data processing engines;
• wherein the second partition includes one or more second data processing engines of the plurality of data processing engines;
• and
• wherein each partition is configured to implement an application that executes independently of the other partition.

A System-on-Chip, comprising:

• a plurality of master circuits;
• a plurality of slave circuits;
• interconnect circuitry coupling the plurality of master circuits with the plurality of slave circuits;
• a plurality of system-management identifier (SMID) circuits coupled to the interconnect circuitry and respective ones of the plurality of master circuits, wherein each SMID circuit is configured to insert a system management identifier into transactions received from the respective master circuit coupled thereto prior to the transactions entering the interconnect circuitry;
• and
• a plurality of programmable protection circuits (PPCs) coupled to the interconnect circuitry and respective ones of the plurality of slave circuits, wherein each PPC allows only transactions with allowed system management identifiers to pass to the respective slave circuit coupled thereto.