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US 2023/0276367 A1Published application
Power management integrated circuit, power management method, mobile device and clock adjusting method
AssigneeSamsung Electronics Co., Ltd.
InventorsJUNGHUN HEO, YOUNGDUK KIM, JOONSEOK KIM, DONGSUK SHIN
Life of this patent
Estimating the term…
Abstract
A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.
Claims20
A system-on-chip (SOC) comprising:
- a clock divider configured to receive a source clock and to generate an operating clock by dividing the source clock, the source clock being externally provided;
- a central processing unit (CPU) configured to receive the operating clock and to operate in response to the operating clock;
- and
- an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided,
- wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the operating clock having a first frequency in response to receiving the first alarm signal, and to generate the operating clock having a second frequency in response to receiving the second alarm signal, the second frequency being less than the first frequency.
2 more elements
A system-on-chip (SOC) comprising:
- a clock divider configured to receive a source clock and to generate an operating clock by dividing the source clock, the source clock being externally provided;
- a central processing unit (CPU) configured to receive the operating clock and to operate in response to the operating clock;
- an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided;
- and
- a control unit configured to generate a power management information indicating a level of a voltage in response to the second alarm signal, the power management information being communicated with an external device,
- wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the operating clock having a first frequency in response to receiving the first alarm signal, and to generate the operating clock having a second frequency in response to receiving the second alarm signal, the second frequency being less than the first frequency.
3 more elements
A system-on-chip (SOC) comprising:
- a clock divider configured to receive a source clock, to generate a first operating clock by dividing the source clock, and to generate a second operating clock by dividing the source clock, the source clock being externally provided;
- a central processing unit (CPU) configured to receive the first operating clock and to operate in response to the first operating clock;
- a graphics processing unit (GPU) configured to receive the second operating clock and to operate in response to the second operating clock;
- an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided,
- wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the first operating clock having a first frequency in response to receiving the first alarm signal, to generate the first operating clock having a second frequency in response to receiving the second alarm signal, to generate the second operating clock having a third frequency in response to receiving the first alarm signal, and to generate the second operating clock having a fourth frequency in response to receiving the second alarm signal, the second frequency and the fourth frequency being less than the first frequency and the third frequency respectively.
2 more elements
Dependencies are inferred from the claim text.