Gaa ldmos structure for hv operation

An integrated circuit (IC) device, comprising:

• a shallow trench isolation (STI) region;
• and
• a transistor having, an inner terminal region, a channel, an outer terminal region, a gate electrode, and a drift region;
• wherein the inner terminal region is above the channel;
• the gate electrode surrounds the channel;
• the STI region surrounds the gate electrode;
• the outer terminal region is outside the STI region;
• the drift region begins underneath the channel, goes underneath the STI region, and extends to the outer terminal region;
• one of the inner terminal region and the outer terminal region is operative as a source;
• an opposite one of the inner terminal region and the outer terminal region is operative as a drain;
• the inner terminal region, the outer terminal region, and the drift region are semiconductor regions with a first doping type;
• and
• the channel is a semiconductor region with a second doping type, which is opposite the first doping type.

A method comprising:

• forming a loop-shaped shallow trench isolation (STI) region within a semiconductor substrate;
• etching away a portion of the loop-shaped STI region to form a loop-shaped trench comprising an outer sidewall that is provided by the loop-shaped STI region and an inner sidewall that is provided by the semiconductor substrate;
• forming a gate oxide on the inner sidewall;
• filling the loop-shaped trench with a conductive material;
• doping a portion of the semiconductor substrate having a first doping type and disposed within the loop-shaped STI region to form a well having a second doping type, wherein the second doping type is opposite the first doping type and a depth of the well is less than a depth of the loop-shaped STI region;
• and
• doping a portion of the semiconductor substrate directly over the well to form a heavily doped region having the first doping type.