Layout Structure of High-Drive-Multiple Standard Cell

A layout structure of a high-drive-multiple standard cell library, wherein the layout structure of the high-drive-multiple standard cell library at least comprises:

• a power line track disposed in the middle of a standard cell along a length direction thereof, a length of the power line track being in flush with a width of the standard cell,
• two ends of the power line track being respectively provided with first-layer metal wires, a length direction of the first-layer metal wires being along the length direction of the standard cell, an intermediate wiring of the power line track being realized through a metal wire other than the first-layer metal wires;
• ground wires located at topmost and bottommost positions of the standard cell, the ground wires being connected to the first-layer metal wires;
• PMOS transistors located directly below the power line track;
• and
• NMOS transistors located at upper and lower ends of the standard cell and adjacent to the ground wires.