Process Method for Improving Reliability of Metal Gate High-Voltage Device

A process method for improving reliability of a metal gate high-voltage device, wherein the process method for improving the reliability of the metal gate high-voltage device at least comprises:

• step 1:
• providing a semiconductor structure, the semiconductor structure comprising a high-voltage device active area;
• a gate oxide layer formed over the high-voltage device active area;
• and stack layers formed over the gate oxide layer and spaced apart from each other, regions between the stack layers being slot regions;
• step 2:
• depositing an SiCN layer to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers;
• step 3:
• depositing a high aspect ratio process (HARP) layer to cover the SiCN layer;
• step 4:
• covering the HARP layer over the stack layers and the slot regions with a photoresist, sequentially performing photolithography and etching to open the HARP layer over the stack layers, and reserving the photoresist in the slot regions;
• step 5:
• removing the HARP layer over the stack layers outside the slot regions;
• step 6:
• repeating steps 3 to step 5 for many times until the slot regions are filled with the HARP layer;
• and
• step 7:
• performing etching to remove the SiCN layer over the stack layers.