Semiconductor memory device, electronic device and method for setting the same

A method for setting a semiconductor memory device, the method comprising:

• reading, by a host, process information from the semiconductor memory device, the process information being programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device;
• performing, by the host, a determination on whether the process information indicates a legacy process or an enhanced process which provides higher device performance than the legacy process;
• selecting, by the host, a target operation mode from among a plurality of operation modes, depending on the determination;
• and
• setting, by the host, an operation mode of the semiconductor memory device based on the selected target operation mode,
• wherein:
• the plurality of operation modes define a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command,
• the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and
• the method further comprises selecting, by the host, a first operation mode corresponding to the first latency from among the plurality of operation modes in response to the process information indicating the enhanced process as the target operation mode, and selecting, by the host, a second operation mode corresponding to the second latency from among the plurality of operation modes in response to the process information indicating the legacy process as the target operation mode.

A semiconductor memory device, comprising:

• a cell array including a plurality of DRAM cells to store data;
• a peripheral circuit configured to write data in the cell array, or to sense and output data stored in the cell array;
• and
• a mode register set circuit configured to output process information about the peripheral circuit to a host, and to set a target output latency of data, from among a plurality of respectively different latencies, in response to a mode register write request from the host, wherein:
• the process information is programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device and indicates whether the process used to manufacture the semiconductor memory device is a legacy process or an enhanced process which provides higher device performance than the legacy process,
• the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and
• the mode register set circuit is configured to, in response to the mode register write request from the host, set a first output latency of data according to the first latency in response to the process information indicating the enhanced process as the target output latency, and set a second output latency of data according to the second latency in response to the process information indicating the legacy process as the target output latency.