System on chip, bus power gating method thereof, and bus power gating system
AssigneeSamsung Electronics Co., Ltd.
InventorsIksu LEE, Jongsung KANG, Junghun HEO
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Abstract
A power gating method of a system on chip includes transferring a first control signal to a bus by using a power management unit (PMU), transferring a response signal to the PMU by using the bus, in response to the first control signal, moving a transaction to a light bus circuit by using the bus, and transferring a second control signal to a power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
Claims20
A power gating method of a system on chip including a power management unit (PMU), a power control circuit, and a bus including a main bus circuit and a light bus circuit, the power gating method comprising:
- transferring a first control signal to the bus by using the PMU;
- transferring a response signal to the PMU by using the bus, in response to the first control signal;
- moving a transaction to the light bus circuit by using the bus;
- and
- transferring a second control signal to the power control circuit by using the PMU to adjust power supplied to the bus, based on the response signal.
A system on chip comprising:
- a bus including a main bus circuit and a light bus circuit, the bus being configured to process a transaction by using the main bus circuit and the light bus circuit and allow a pending transaction to be processed by the light bus circuit based on a transaction threshold value of the light bus circuit;
- a power control circuit including a main bus power switch, a light bus power switch, and a power path controller, the power control circuit being configured to control power supplied to the bus;
- and
- a power management unit (PMU) configured to generate a first control signal and a second control signal based on an amount of transactions, transfer the first control signal to the bus to control an operation of the bus, and transfer the second control signal to the power control circuit to control an operation of the power control circuit.
A bus comprising:
- a main bus circuit and a light bus circuit each configured to process a transaction of the bus, wherein,
- in response to an amount of transactions being greater than or equal to a transaction threshold value of the light bus circuit, the bus is configured to process the transaction by using the main bus circuit and the light bus circuit, and
- in response to the amount of transactions being less than the transaction threshold value, the bus is configured to process a pending transaction by using the light bus circuit.
Dependencies are inferred from the claim text.