Design system, design method and method of manufacture of semiconductor device

A design system for a semiconductor device, the design system comprising:

• a storage device configured to store information including procedures;
• and
• a processor configured to access the storage device and execute the procedures, and
• wherein the procedures includes a design module configured to:
• receive input data defining the semiconductor device;
• obtain a first layout of the semiconductor device by performing a placement and routing in response to the input data, the first layout including a plurality of blocks, a plurality of standard cells, a plurality of decoupling capacitor cells, a plurality of filler cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of non-clock signal wirings;
• set a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells;
• and
• obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region.

A method of designing a layout of a semiconductor device, the method comprising:

• receiving input data defining the semiconductor device;
• obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data, wherein the obtaining of the first layout of the semiconductor device includes:
• developing a floor plan for a plurality of blocks, a plurality of standard cells, a plurality of decoupling capacitor cells and a plurality of filler cells included in the semiconductor device;
• developing a power plan for a plurality of power wirings and a plurality of ground wirings included in the semiconductor device;
• performing a placement of elements included in the plurality of blocks and the plurality of standard cells;
• performing a clock tree synthesis (CTS) for clock signals provided to the elements via a plurality of clock wirings included in the semiconductor device;
• and
• performing a routing of non-clock signals provided to the elements via a plurality of non-clock signal wirings included in the semiconductor device;
• verifying results of the placement and routing;
• while verifying results of the placement and routing, setting a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells and the plurality of standard cells is not disposed in the target region;
• and
• while verifying results of the placement and routing, obtaining a second layout of the semiconductor device by replacing the first decoupling capacitor cell in the target region with a second decoupling capacitor cell having a structure different from that of the first decoupling capacitor cell,
• wherein the target region is a sub-region of the semiconductor device proximate to at least one of a corner of the semiconductor device and an edge portion of the semiconductor device, and
• the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes:
• removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell;
• arranging the second decoupling capacitor cell in the target region, and
• electrically connecting the second decoupling capacitor cell to a second power wiring and a second ground wiring external to the target region.