US 2023/0267259 A1 · SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE

Abstract

Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

Claims20

Dependent claims

A system comprising:

a memory storing a cell library comprising sets of cells with all cells in a set of cells having different combinations of cell boundary isolation structures associated with different delay values,
wherein the memory further stores a layout for a logic circuit,
wherein the layout comprises multiple cells from the cell library representing the logic circuit, and
wherein the memory further stores timing constraints for the logic circuit;
and
a processor in communication with the memory and generating an updated layout by replacing a cell of the multiple cells in the layout with another cell from a same set of cells in the cell library to facilitate fixing of a violation of a timing constraint.

3 more elements

A method comprising:

accessing, by a processor from memory, a cell library, a layout for a logic circuit, and timing constraints for the logic circuit,
wherein the cell library comprises sets of cells with all cells in a set of cells having different combinations of cell boundary isolation structures associated with different delay values, and
wherein the layout comprises multiple cells from the cell library representing the logic circuit;
and
generating, by the processor, an updated layout by replacing a cell of the multiple cells in the layout with another cell from a same set of cells in the cell library to facilitate fixing of a violation of a timing constraint.

2 more elements

Dependencies are inferred from the claim text.

System and method employing power-optimized timing closure

Life of this patent

System and method employing power-optimized timing closure

Life of this patent

Abstract

Claims20