Chip, Method, Accelerator, and System for Pooling Operation

A method for pooling operation, comprising:

• outputting by a demultiplexer a first matrix from a first input terminal of the demultiplexer via a first output terminal of the demultiplexer or via a second output terminal of the demultiplexer in response to a first control signal;
• performing multiple outputs by a first memory to output each element of the first matrix stored by the first memory and output a column of elements of the first matrix in parallel each time in response to a second control signal in the case where the first matrix is output via the first output terminal, the first memory being connected to the first output terminal;
• outputting serially by a second memory each element of a second matrix in the first matrix stored by the second memory in response to a third control signal in the case where the first matrix is output via the second output terminal, the second memory being connected to the second output terminal;
• and
• performing a pooling operation by a computation circuit on the second matrix from the first memory or the second memory to obtain an operation result in response to a fourth control signal.